1. Technical Field
The invention relates to integrated circuit design. More particularly, the invention relates to the use of an improved time budgeting technique during the design of integrated circuits.
2. Description of the Prior Art
FIG. 1 is a block schematic diagram of a design process 10 that employs time budgeting techniques during the synthesis of a complex integrated circuit. Time budgeting is very important during the design of complex integrated circuits. In the early part of the design cycle, it is important to set realistic constraints for each separate design module. In the late part of the design cycle, convergence issues dominate. Time budgeting is used during the design of integrated circuits because known circuit synthesis techniques are limited with regard to the complexity of circuits that can be processed in a single run. Thus, a complex circuit design is typically subdivided into a plurality of synthesizable sub-modules. A time budgeting algorithm 13 is run on the complete design to generate constraints for the sub-modules. The sub-modules are then run through synthesis separately 15. The resulting modified sub-modules are then reassembled 16 and the whole process is repeated.
The initial netlist 11 that is passed into the flow is a mapped netlist. It is possible to use an area optimized and mapped circuit as the starting point for the flow. At the initial stages, it is necessary that the budgeting algorithm provide realistic constraints 14 because over constraining the synthesis runs may result in a defective netlist that cannot be recovered during subsequent passes through the flow. In the final stages, it is important that the design optimization process converges and that the synthesis runs on the sub-modules at least start out working on the globally critical paths.
One of techniques that is currently being used for time budgeting is referred to as the xe2x80x9ccharacterizexe2x80x9d technique. The characterize technique generates constraints for a sub-module based upon a timing analysis that is run on the entire netlist. Specifically, the arrival time constraint for an input port of a sub-module is set to the arrival time for the port for the global timing analysis run. Similarly, the required time constraint for an output port of a sub-module is set to the required time computed in the global timing analysis run at the port.
The characterize constraint generation process makes an inherent assumption that all of the sub-modules, except for the module for which constraints are being generated, are essentially fixed. This is a pessimistic assumption that effectively results in over constraining the sub-module. Thus, this technique does not perform very well during the initial phases of the design.
The characterize technique also does not guarantee convergence, as is shown on FIGS. 2a and 2b, which provide block schematic diagrams that illustrate the characterize technique as used for time budgeting during the design of an integrated circuit. The whole design consists of three identical modules 20, 22, 24 that are coupled in a linear fashion, as shown on FIG. 2(a). As shown, the path spanning across the sub-modules 25 has a slack value of xe2x88x923. The flop to flop path 26 in each sub-module has a slack value of xe2x88x924.
When characterize is used as the time budgeting algorithm, the slacks of the paths in the sub-module synthesis runs start out with the same value as for the slacks in the global timing analysis run. Thus, it is possible that the flop to flop path may be improved by a value of 0.5 at the expense of increasing the delay of the sub-path that is part of the longer path by a value of 0.5. As a result, the local slack 28 (see FIG. 2b) at end of the synthesis run has a value of xe2x88x923.5, which is an improvement from the previous value xe2x88x924. However, when the designs are reassembled (see FIG. 2b), the long path 27 shows a slack value of xe2x88x924.5, which is worse than the worst slack in the previous run, i.e. a slack value of xe2x88x924.
The example shown on FIGS. 2a and 2b illustrates that the characterize technique could result in convergence problems and that the worst slack value may not be improved in a monotonic fashion. The characterize technique, however, does produce synthesis runs of the sub-modules that at least start out working on the globally critical paths because the slacks seen in the sub-module runs start out being the same as those of the global timing analysis run.
It would be advantageous to provide a time budgeting technique that optimizes constraints for each sub-module during an early design phase, while guaranteeing convergence during a late design phase.
The invention provides two techniques that are useful during the early and late design phases of an integrated circuit, respectively. During the early design phase, both positive and negative slack paths are budgeted. This technique provides the advantage over the prior art that a positive slack path never turns into a negative slack path after budget generation. Also, if all of the budget constraints are met by resynthesis for all of the modules, then the technique guarantees that the final design, when assembled, meets all constraints.
During the late design phase, convergence is guaranteed. Further, synthesis runs for the sub-modules focus initially on the worst critical path.